Digital multiplexing and demultiplexing system

ABSTRACT

A digital multiplexing and demultiplexing system for time division multiplexing a number of incoming plesiosynchronous low rate component signals and a number of incoming plesiosynchronous intermediate rate component signals into an outgoing single high rate signal. A first multiplexing stage time stores and stuffs the low rate component signals and multiplexes them into synchronous intermediate rate signals. A second multiplexing stage stores and stuffs the plesiosynchronous and synchronous intermediate rate signals and multiplexes them into the outgoing high rate signal.

CROSS REFERENCE TO RELATED APPLICATIONS

Applicants hereby make cross references to their French patentapplication No. PV 77 22880 filed July 26, 1977 and claim prioritythereunder folowing the provisions of 35 U.S.C. 119.

BACKGROUND OF THE INVENTION

1. Field of the invention

This invention relates to a digital multiplexing and demultiplexingsystem.

2. Description of the Prior Art

Digital multiplexing and demultiplexing are a concept known in the priorart and has been described, for instance, in paper entitled"Experimental 224 Mb/s digital multiplexer-demultiplexer using pulsestuffing synchronization" by F. J. WITT in the "Bell System TechnicalJournal", November 1965, pages 1843-1885 and in a paper entitled"Digital multiplexing systems" by Yvon MADEC in "Echo des Recherches",January 1973, pages 59-67. Digital multiplexing systems or multiplexersprovide multiplexing by the time slotting of component digital signalsof one rate into a single digital resulting signal of a higher rate.Digital demultiplexing systems or demultiplexers provide the converseoperation. The resulting signal must contain a special recurrent signalwhich is called the framing signal and which gives the demultiplexer areference.

In the case of an asynchronous network the clocks of the componentsignals are independent, but may be plesiosynchronous, i.e. they allhave the same rated frequency and variations therearound are confinedwithin specified limits. Before time multiplexing can be carried out thecomponent signals must be made synchronous with one another. The usualprocedure is to equalize the rates upwards converting each componentsignal to a bit rate slightly above its nominal rate. The differencebetween the rates is filled up in the converted signal by additionalbits called stuffing bits. The multiplexing of the stuffed signals iscalled positive stuffing multiplexing.

The demultiplexer is also required to recognize and remove the stuffingbits associated with each component signal so as to restore it properly.Accordingly, the stuffing bits, if present, have a definite position inthe frame (the frame is the interval separated by two consecutiveframing signals) and their presence or absence is indicated by thelogical value of special (systematically inserted) filling bits called"stuffing indication bits".

If N denotes the number of plesiosynchronous component signals to bemultiplexed, F_(e) denotes their nominal rate and F_(s) >NF_(e) denotesthe nominal rate of the resulting signal, then:

    F.sub.s =NF.sub.e (1+ε)(1+P/Q)                     (1)

where Q denotes the number of information bits per frame, P denotes thenumber of filling bits (framing, stuffing indication and, whereapplicable, service bits) per frame and F_(d) =εF_(e) denotes thenominal stuffing rate.

A multiplexing and demultiplexing system allots to a predeterminednumber of incoming component digital channels at a predetermined rate asingle digital resulting channel at a different predetermined rate. Therates of the digital channels are defined by national telecommunicationauthorities and are called master rates; some rates also are definedinternationally. One passes generally from a low master rate to the highmaster rate immediately superior directly by means of a multiplexingstage, there being a single relationship between the master rates of thecomponent signals and the resulting signal.

Such a multiplexing and demultiplexing operation is disclosed in U.S.Pat. No. 3,987,248 issued Oct. 19, 1976 to Frederic M. Platet, Yvon N.Madec and Patrick E. Boutmy. In this patent, incoming digital componentsignals are time division multiplexed into a digital resulting signalhaving a high rate. Thus sixteen plesiosynchronous incoming component 8Mb/s signals are time multiplexed into a resulting digital signal havingthe 140 Mb/s high rate. This resulting signal can be demultiplexed, ofcourse, into sixteen outgoing digital component 8 Mb/s signals but alsointo four 34 Mb/s intermediate rate digital signals. However, it is notpossible to time multiplex at the same time the plesiosynchronous 8 Mb/slow rate component signals and one or several plesiosynchronous 34 Mb/sintermediate rate component signals.

OBJECT OF THE INVENTION

The object of the present invention is to provide a digital multiplexingand demultiplexing system for multiplexing a number of plesiosynchronouscomponent signals having a nominal low rate and a number ofplesiosynchronous component signals having a nominal intermediate rateinto a single resulting signal having a nominal high rate which isslightly multiple of the nominal low and intermediate rates.

SUMMARY OF THE INVENTION

According to this invention, there is provided a digital multiplexingand demultiplexing system in which a number of incomingplesiosynchronous low rate component signals having respectiveoriginating rates departing from a predetermined nominal low rate whichis slightly higher than all said originating rates are time multiplexedbit by bit into synchronous intermediate rate signals and a number ofincoming plesiosynchronous intermediate rate component signals havingrespective originating rates departing from a predetermined nominalintermediate rate which is slightly higher than said originating ratesare time multiplexed bit by bit with said synchronous intermediate ratesignals into an outgoing single rate signal having a high rate which isslightly multiple of said originating intermediate rates, said low ratesignals and said plesiosynchronous intermediate rate signals comprisingonly information bits and said synchronous intermediate rate signals andsaid high rate signal comprising information bits, stuffing bits andfilling bits including framing bits, service bits and stuffingindication bits arranged in predetermined bit positions in frames, thesystem comprising:

a--first means for storing said low rate component signals;

b--means for stuffing said low rate component signals in dependence uponthe difference between their own originating respective low rates andsaid nominal low rate;

c--multiplexing means receiving the signals read out of said storingmeans and multiplexing said nominal low rate stuffed signals into framesof said synchronous intermediate rate signals;

d--means for inserting into said synchronous intermediate rate signals afirst number of filling bits in bit positions of predetermined addressesof the frame thereof and thereby forming synchronous intermediate ratefilled signals;

e--second means for storing said synchronous intermediate rate filledsignals;

f--third means for storing said plesiosynchronous intermediate ratecomponent signals;

g--means for stuffing said synchronous intermediate rate filled signalsand said plesiosynchronous intermediate rate component signals independence upon the difference between their own originating respectiveintermediate rates and said nominal intermediate rate;

h--multiplexing means receiving the signals read out of said second andthird storing means and multiplexing said nominal intermediate ratestuffed signals into frames of said high rate signal; and

i--means for inserting into said high rate signal a second number offilling bits in bit positions of predetermined addresses of the framethereof and thereby forming a high rate filled signal.

A digital multiplexing system embodying this invention provides adigital resulting signal having a 34 Mb/s high rate from timemultiplexing of sixteen plesiosynchronous digital incoming componentsignals having a 2 Mb/s low rate but also from time multiplexing of:

twelve plesiosynchronous incoming 2 Mb/s signals and one incoming 8 Mb/ssignal;

eight plesiosynchronous incoming 2 Mb/s signals and twoplesiosynchronous incoming 8 Mb/s signals; or

four plesiosynchronous incoming 2 Mb/s signals and threeplesiosynchronous incoming 8 Mb/s signals.

In each case, the digital time demultiplexing system embodying thisinvention which is associated with the corresponding multiplexing systemembodying this invention permits to recovery at the receiver theoutgoing component signals having rates equal to these of the incomingcomponent signals at the transmitter.

Bit stuffing is an operation associated with time division multiplexingto be used each time the signals to be time division multiplexedoriginate from unsynchronized sources. In the case of two multiplexingstages, for example a first multiplexing stage of 8 into 34 Mb/s and asecond multiplexing stage of 34 into 140 Mb/s or a first multiplexingstage of 2 into 8 Mb/s and a second multiplexing stage of 8 into 34Mb/s, there are provided two groups of storage and stuffing circuits.The first group stuffes the plesiosynchronous low rate component signalshaving 2 or 8 Mb/s rate and the second group stuffes the intermediaterate signals having 8 or 34 Mb/s rate.

When the high rate signal having a 34 or 140 Mb/s rate is provided fromtime multiplexing of synchronous intermediate rate signals which areoriginated from time multiplexing of plesiosynchronous incoming low ratesignals, and of plesiosynchronous incoming intermediate rate signals,the multiplesing system of this invention stuffes the synchronousintermediate rate signals as well as the plesiosynchronous intermediaterate signals into synchronous stuffed intermediate signals.Nevertheless, when plesiosynchronous incoming low rate signals are onlytime multiplexed it is necessary to stuff the resulting synchronousintermediate rate signals. In fact, if F_(e) denotes the nominalintermediate rate and F_(s) >NF_(e) denotes the nominal high rate of theresulting signal for N plesiosynchronous and/or synchronous intermediatesignals to be multiplexed, then:

    F.sub.s /N(1+P/Q)>F.sub.e

and the resulting high rate signal 34 or 140 Mb/s can be demultiplexedby means of a demultiplexing system 34-8 Mb/s or 140-34 Mb/s for thecountries having the 34 or 8 Mb/s rate as intermediate master rate.

The foregoing and other objects, features and advantages of the presentinvention will be become apparent from the following more particulardescription of preferred embodiments of the invention as illustrated inthe accompanying drawing.

BRIEF DESCRIPTION OF THE DRAWING

FIG. 1 shows a prior art two-stage digital multiplexing system;

FIG. 2 shows a prior art two-stage digital demultiplexing system;

FIG. 3 is a chart illustrating one frame of a high rate 34 Mb/s signal;

FIG. 4 is a chart illustrating one frame of an intermediate rate 8 Mb/ssignal;

FIG. 5 shows a two-stage digital multiplexing system embodying thisinvention;

FIG. 6 shows a two-stage digital demultiplexing system embodying thisinvention;

FIG. 7 is a schematic block diagram illustrating a two-stage system formultiplexing and demultiplexing sixteen digital component 2 Mb/s signalsinto a digital resulting 34 Mb/s signal according to this invention; and

FIG. 8 is a schematic block diagram illustrating a two-stage system formultiplexing and demultiplexing eight digital component 2 Mb/s signalsand two digital component 8 Mb/s signals into a digital resulting 34Mb/s signal.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 illustrates a prior art digital multiplexer having twomultiplexing stages I and II. 1₀ through 1₁₅ designate sixteen incomingchannels 1₀ through 1₁₅ having a nominal 2.048 Mb/s rate. In a firstmultiplexing stage I the incoming channels extend to code conversion andclock signal extraction circuits 2₀ through 2₁₅ respectively each havingtwo output terminals, one for the digital information and the other forthe clock signal. The code conversion and clock signal extractioncircuits 2₀ through 2₁₅ perform in known manner the distinct functionsof converting the incoming signals from the code used on the incomingchannels 1₀ through 1₁₅ to the binary code used by the digitalmultiplexer, of shaping the incoming channel signals and of extractingthe clock signal. By way of example, the first function is carried outby a HDB3-binary transcoder. The HDB₃ code is well known in the art andis for example disclosed in the paper of the C.C.I.T.T., SpecialCommittee D, Contribution No. 33, 23rd September 1969. Each codeconversion and clock signal extraction circuit 2₀ through 2₁₅ isconnected to a respective storage and positive stuffing circuit 3₀through 3₁₅.

Only the circuit 3₀ is shown in detail in FIG. 1. It comprises a bufferstore 30₀ having a write-in input terminal 300₀ connected to the digitalinformation output terminal of circuit 2₀, and a write-in progressioninput terminal 301₀ connected to the clock signal output terminal ofcircuit 2₀. Store 30₀ comprises a read output terminal 302₀ and a readprogression input terminal 303₀, the latter receiving a signal from atime 7₀,3 by way of a read control circuit 31₀. The write-in addressoutput terminal and the read-out address output terminal of the bufferstore 30₀ are connected to a phase comparator 32₀ whose output isconnected to a stuffing authorisation circuit 33₀. This stuffingauthorisation circuit 33₀ is connected to the time base 7₀,3 which viaterminal 304₀ transmits to circuit 33₀ clock pulses coinciding with thebit positions in the frame assigned to the stuffing bits. Circuit 33₀ isconnected to the read control circuit 31₀ which receives a readingcontrol signal from the time base 7₀,3 via terminal 303₀. Read controlcircuit 31₀ is inhibited when it receives stuffing authorisationsignals. The read output terminal of the buffer store is connected to astuffing indication bit insertion circuit 34₀ which inserts the stuffingindication bits into the stuffed channel in accordance with the orderreceived from the circuit 33₀.

The digital information output terminals such as 302₀ of the storage andpositive stuffing circuits 3₀ through 3₃ are connected to the inputs ofa multiplexer 4₀,3 controlled by time base 7₀,3. The single output ofthe multiplexer 4₀,3 is connected to a code conversion and retimingcircuit 5₀,3. The multiplexers 4₀,3, 4₄,7, 4₈,11 and 4₁₂,15 areparallel-to-series converters such as shift registers which receive thelow-rate signals for multiplexing in parallel and deliver them in seriesat a high rate which in the present case is the intermediate rate whileinserting the framing signal at the beginning of each frame. Eachmultiplexer receives from its own time base the 2 Mb/s sync signal andthe 8 Mb/s sync signal. Multiplexer 4₀,3 also comprises AND gate for theinsertion into the frame of framing, stuffing indication and servicebits.

At the output of the first multiplexing stage I there are the codeconversion and retiming circuits 5₀,3, 5₄,7, 5₈,11 and 5₁₂,15. Extendingfrom the code conversion and retiming circuits are 8 Mb/s digitalchannels 6₀,3, 6₄,7, 6₈,11 and 6₁₂,15. The code conversion and retimingcircuits perform the functions of converting from the binary code usedby the digital multiplexers to the code used by channels 6₀,3 through6₁₂,15 by way of a binary-HDB 3 transcoder, of shaping the multiplexedsignals, and of retiming.

The output digital channels of the first multiplexing stage I areconnected to code conversion and clock signal extraction circuits 12₀through 12₃ of a second multiplexing stage II. The second stage II isvery similar to the first stage I except that it multiplexes fourdigital input channels into a single digital output channel instead ofmultiplexing four times four channels. In addition to the codeconversion and clock signal extraction circuits 12₀ through 12₃ thestage II comprises storage and positive stuffing circuits 13₀ through13₃, a multiplexer 14, a code conversion and retiming circuit 15 and atime base 17. Output channel 16 has a rate of 34 Mb/s.

Referring now to FIG. 2, a prior art digital demultiplexer has a 34 Mb/sdigital channel 20 which extends in the first demultiplexing stage IIIto a code conversion and clock signal extraction circuit 21 deliveringthe digital information signal and the clock signal on separate outputterminals. The information output terminal of the circuit 21 isconnected to a framing signal recognition circuit 24 which synchronizesa time base 27. The information signal is applied to the demultiplexer22 which has four output terminals 22₀ through 22₃, and the timingsignals goes to the time base 27. Each output terminal of thedemultiplexer 22 is connected to a respective storage and unstuffingcircuits 23₀ through 23₃. Only the circuit 23₀ is shown in detail inFIG. 2. The circuit 23₀ comprises a buffer store 230₀ having a write-ininput terminal 2300₀ connected to the demultiplexer output terminal 22₀and a write-in progression input terminal 2301₀ connected to time base27 by way of a write-in control circuit 231₀. The write-in controlcircuit 231₀ also receives a signal from a stuffing recognition circuit234₀ which is also connected to the write-in input terminal 2300₀ andwhich receives from the time base 27 via the input terminal 2304₀ astuffing indication bit address signal. The buffer store can have e.g.eight stages. The buffer store 230₀ comprises a read-out output terminal2302₀ and a read-out progression input terminal 2303₀. The write-in andread-out address output terminals of the buffer store 230₀ are connectedto a phase comparator 232₀ whose output terminal is connected to acircuit 233₀ comprising a low-pass filter and a voltage-controlledoscillator. The output terminal of the oscillator controls the readingof the buffer store.

The digital information output terminals such as 2303₀ of the storageand unstuffing circuits 23₀ through 23₃ are connected to code conversionand retiming circuits 25₀ through 25₃ which receive the 8 Mb/s clocksignal from each voltage-controlled oscillator 233₀ through 233₃respectively via an output terminal such as 2303₀. 8 Mb/s digitalchannels 26₀ through 26₃ extend from the code conversion and retimingcircuits 25₀ through 25₃.

The digital output channels 26₀ through 26₃ of the first demultiplexingstage III are connected to code conversion and clock signal extractioncircuits 41₀,3 through 41₁₂,15 of the second demultiplexing stage IV.The same is very similar to the first demultiplexing stage III exceptthat it demultiplexes four digital input channels into sixteen digitaloutput channels instead of demultiplexing a single digital input channelinto four digital output channels. In addition to the code conversionand clock signal extraction circuits 41₀,3, 41₄,7, 41₈,11 and 41₁₂,15,it comprises four demultiplexers 42₀,3, 42₄,7, 42₈,11 and 42₁₂,15,sixteen storage and unstuffing circuits 43₀ through 43₁₅ and sixteencode conversion and retiming circuits 45₀ through 45₁₅. Output channels46₀ through 46₁₅ of the latter circuits have a rate of 2 Mb/s. Timebases 47₀,3, 47₄,7, 47₈,11 and 47₁₂,15 control the demultiplexers andthe storage and unstuffing circuits.

Before describing the digital multiplexer and demultiplexer of thesystem embodying this invention, a description will be given ofmultiplex frame structures of the 8 Mb/s and 34 Mb/s signals to assistunderstanding of the structure and operation of the multiplexer anddemultiplexer embodying the invention.

FIG. 3 shows the structure of a 34 Mb/s digital signal recommended bythe C.C.I.T.T. The frame comprises four sectors, numbered 0 to 3, eachcontaining 384 bits, every sector except the first starting with fourstuffing indications bits (SIB). The stuffing bits (SB), if any, are inthe four bit positions following the stuffing indication bits of thefourth section No. 3. The framing bits (FB) are the first ten bits ofthe first sector and are followed by two service bits (SeB). In a frame,the number of filling bits which correspond to ten framing bits (FB),two service bits (SeB) and 3×4=12 stuffing indication bits (SIB) isequal to P=24, the number of stuffing bits is equal to 4 and the numberof information bits originating from 8 Mb/s signal isQ=(384×4)-(24+4)=1508 in a 1536-bit frame.

A bit position in the 1536-bit frame is defined by an address havingthree address parts. A first address part is equal to the remainder,between 0 and 3, of the division of the bit position number, between 0and 1535, in the frame by 4. This first address indicates the number 0,1, 2 or 3 of the incoming 8 Mb/s channels 6₀,3, 6₄,7, 6₈,11 or 6₁₂,15 towhich the considered bit belongs. A second address part is equal to theremainder, between 0 and 95, of the division of the quotient, between 0and 383, of the preceding division by 96. This second address partindicates the number, between 0 and 95, of the 4-bit word in the sectorto which the considered bit belongs. Finally, the third address part isequal to the remainder, between 0 and 3, of the division of thequotient, between 0 and 3, of the last preceding division by 4. Thisthird address part indicates the number, between 0 and 3, of the sectorto which the considered bit belongs. For example, the first stuffing bitwhich has the position number 1156 in the 1536 bit frame is defined bythe three following address parts:

1156=4×289+0; first address part=0

289=96×3+1; second address part=1

3=4×0+3: third address part=3

Thus the bit of position No. 1156 belongs to the incoming 8 Mb/s channelNo. 0 and the 4-bit word No. 1 of the sector No. 3.

FIG. 4 illustrates the structure of a 8 Mb/s digital signal recommendedby the C.C.I.T.T. The frame comprises four sectors, numbered 0 to 3,each containing 212 bits, every sector except the first starting withfour stuffing indication bits (SIB). The stuffing bits (SB), if any, arein the four bit positions following the stuffing indication bits of thefourth sector No. 3. The framing bits (FB) are the first ten bits of thefirst sector and are followed by the service bits (SeB). In a 848-bitframe, the number of filling bits which correspond to ten framing bits(FB), two service bits (SEB) and 3×4=12 stuffing indication bits (SIB)is equal to P=24 and the number of stuffing bits is equal to 4. Thenumber of information bits originating from four 2 Mb/s signals isQ=(212×4)-(24+4)=820 in a 848-bit frame.

A bit position in the 848-bit frame is defined by an address havingthree address parts in a similar manner to bit address in the preceding1536-bit frame. A first address part is equal to the remainder, between0 and 3, of the division of the bit position number, between 0 and 847,in the 848-bit frame by 4. This first address part indicates the number0, 1, 2 or 3 of the four incoming 2 Mb/s channels to which theconsidered bit belongs. A second address part is equal to the remainder,between 0 and 52, of the division of the quotient, between 0 and 211, ofthe preceding division by 53. This second address indicates the number,between 0 and 52, of the 4-bit word in the sector to which theconsidered bit belongs. Finally, the third address part is equal to theremainder, between 0 and 3, of the division of the quotient, between 0and 3, of the last preceding division by 4. This third address partindicates the number, between 0 and 3, of the sector to which theconsidered bit belongs. For example, the first stuffing bit which hasthe position number 640 in the 848-bit frame is defined by the followingaddress parts:

640=4×160+0; first address part=0

160=53×3+1; second address part=1

3=4×0+3; third address part=3

Thus the bit of position No. 640 belongs to the incoming 2 Mb/s channelNo. 0 and the 4-bit word No 1 of the sector No. 3.

The addresses of the first stuffing bit are identical in the 1536-bitframe of the 34 Mb/s digital channel and the 848-bit frame of a 8 Mb/sdigital channel.

Referring to FIG. 5, the digital multiplexing system embodying thepresent invention is distinguished from the prior art multiplexer by themultiplexing of eight plesiosynchronous incoming digital 2,048 Mb/schannels 1₀ through 1₇ instead of sixteen and by the direct receiving oftwo plesiosynchronous incoming digital 8 Mb/s channels 11₂ and 11₃. Inthe first multiplexing stage XI, the two groups of four 2,048 Mb/schannels 1₀ through 1₃ and 1₄ through 1₇ extend to two groups ofcircuits in a similar manner to those shown in FIG. 1. Each group ofcircuits comprises four code conversion and clock signal extractioncircuits 2₀ through 2₃ or 2₄ through 2₇, four storage and positivestuffing circuits 3₀ through 3₃ or 3₄ through 3₇ and a multiplexer 4₀,3or 4₄,7 respectively. The two incoming 8 Mb/s channels 11₁ and 11₃extend to two code conversion and clock signal extraction circuits 12₂and 12₃ which are connected to respective storage and positive stuffingcircuits 13₂ and 13₃ the second multiplexing stage XII.

The two output terminals of the two multiplexers 4₀,3 and 4₄,7 transmittwo synchronous filling 8 Mb/s signals and are connected to respectiveoutput terminals 13000, 13001 of a storage and positive stuffing circuit13 of the second stage XII. Two information output terminals 13020 and13021 of the circuit 13 and the two respective information outputterminals 1302₂, 1302₃ of circuits 13₂ and 13₃ transmit four 8 Mb/sintermediate rate synchronous stuffed signals and are connected to thefour information inputs 1410₀ through 1410₃ of the multiplexer 14 of thesecond stage XII. The information output of the multiplexer 14 transmitsthe 34 Mb/s high rate filled resulting signal and is connected to a codeconversion and retiming circuit (not shown) from which extends theoutput digital channel 16 having a rate of 34 Mb/s.

The storage and stuffing circuits 3₀ through 3₇ of the first stage XIare controlled by a time base 7. The storage and stuffing circuits 13,13₂ and 13₃ of the second stage XII are controlled by a time base 17.

The time base 7 comprises a 8.448 MHz clock 70, a divide-by-4 circuit71, a divide-by-53 circuit 72 and a divide-by-4 circuit 73. The clock 70generates the clock pulses at the nominal intermediate rate F_(s) of theresulting multiplex signal and on the outgoing channel of onemultiplexer 4₀,3 or 4₄,7. The three circuits or frequency dividers 71,72 and 73 deliver pulses at frequencies assigned to the 4-bit words of a848-bit frame, to the 212-bit sectors and to the bits of the 848-bitframe, respectively. These three pulse frequencies are applied to anaddress circuit 75. The output terminal 750 of the circuit 75 deliversreading control signals to the read progression input terminal 303₀ ofthe storage and stuffing circuits such as 3₀. The output terminals 753and 754 of the address circuit 75 deliver the framing bit addresses andthe service bit addresses in the 848-bit frame, or more precisely,respective signal during the time slots corresponding to positions offraming bits and service bits in the 848-bit frame. The address circuit75 also delivers on its output terminal 752 a signal during thetime-slot of a framing bit or a service bit to be inserted in the848-bit frame. Finally, the address circuit 75 provides on the outputterminal 751 a timing signal coinciding with the bit positions in theframe assigned to the stuffing indication bits. The terminal 751 isconnected to the input terminal such as 304₀ of the stuffingauthorization circuits such as 33₀ of the circuits 3₀ through 3₇. Theoutput terminal 752 of the address circuit 75 is connected to AND gatessuch as 41 of the multiplexers 4₀,3 and 4₄,7 to inhibit any bit transferfrom the circuits 3₀ to 3₇ during the insertion of framing bits orservice bits. The output terminals 753 and 754 are connected to themultiplexers 4₀,3 and 4₄,7 to perform the insertion of the framing andservice bits.

The time base 17 comprises a 34.368 MHz clock 170, a divide-by-4 circuit171, a divide-by-96 circuit 172 and a divide-by-4 circuit 173. The clock170 provides the clock pulses at the nominal high rate F_(s) of theresulting multiplex signal on the outgoing channel 16 of the secondmultiplexing stage XII. The three circuits or frequency dividers 171,172 and 173 deliver pulses at frequencies assigned to the 4-bit words ofa 1536-bit frame, to the 384-bit sectors and to the bit of the 1536-bitframe, respectively. These three pulse frequencies are delivered to anaddress circuit 175. The output terminal 1750 of the circuit 175provides reading control signals to the read progression input terminalssuch as 1303 and 1303₂ of the read control circuits such as 131 and 131₂of circuits 13, 13₂ and 13₃. The address circuit 175 delivers on outputterminals 1753 and 1754 to the multiplexer 14 the framing bit addressesand the service bit addresses in the 1536-bit frame during therespective time slots corresponding to positions of framing bits andservice bits so as to insert these bits in the frame. The addresscircuit 175 provides on its output terminal 1752 to the input AND gatessuch as 141 of the multiplexer 14 a signal during the time slot of aframing bit or a service bit to be inserted in the 1536-bit frame. Thislast signal inhibits the bit transmission between the circuits 13, 13₂and 13₃ and the multiplexer 14 during the insertion of a framing bit orservice bit in the 1536-bit frame. A control signal is also deliveredfrom an output terminal 1751 of the address circuit 175 to the inputterminals such as 1304 and 1304₂ of the stuffing authorization circuitssuch as 133 and 133₂ of the storage and stuffing circuits 13, 13₂ and13₃ during the time slots of the stuffing indication bits.

The storage and stuffing circuits 13, 13₂ and 13₃ of the secondmultiplexing stage XII receive the same signals from the time base 17and emit stuffed digital multiplex 8 Mb/s signals having same 848-bitframe structures to the multiplexer 14. The storage and stuffing circuit13 enables simultaneous stuffing of two incoming 8 Mb/s signals whichare synchronous since these signals have been stuffed by means of thesame time base 7. On the contrary, the storage and stuffing circuitssuch as 13₂ and 13₃ are assigned plesiosynchronous incoming component 8Mb/s signals. In the case of the multiplexing of sixteen incomingcomponent 2 Mb/s signals, the storage and stuffing circuits such as 13₂are not provided in accordance with this invention, the four inputterminals 13000 through 13003 of the buffer store 130 and the fouroutput terminals 13020 through 13023 of the stuffing bit insertioncircuit 134 of the circuit 13 being utilized.

FIG. 6 illustrates the demultiplexer of the system embodying theinvention. As compared with the prior art demultiplexer of FIG. 2 thedemultiplexer of this invention also comprises the code conversion andclock signal extraction circuit 21, the demultiplexer 22, the fourstorage and unstuffing circuits 23₀ through 23₃ and the framing signalrecognition circuit 24 in the first demultiplexing stage XIII.

The timing signal output terminal of the circuit 24 is connected to atime base 27 which is similar to the time base 17 of FIG. 5. The timebase 27 comprises a divide-by-4 circuit 271, a divide-by-96 circuit 272and a divide-by-4 circuit 273 which deliver frequencies to an addresscircuit 275. The output terminals 2750 and 2751 of the circuit 275correspond to the terminals 1750 and 1751 of the circuit 175. Theterminal 2750 is connected to the write-in progression input terminalsuch as 2301₀ of the write-in control circuit such as 231₀ of each storeand stuffing circuit 23₀ through 23₃. The terminal 2751 is connected tothe input terminal such as 2304₀ of the stuffing recognition circuitsuch as 234₀ of the circuits 23₀ through 23₃ to delete all the receivedfilling bits per 1536-bit frame of which the addresses are transmittedon the output terminal 2751 of the address circuit 275.

The digital information output terminals such as 2302₀ of the circuits23₀ through 23₃ transmit to a second demultiplexing stage XIV twosynchronous digital 8 Mb/s signals to be demultiplexed and two otherplesiosynchronous outgoing 8 Mb/s signals which are not demultiplexedand are transmitted through code conversion and retiming circuits 25₂and 25₃ of the first stage XIII. Each voltage-controlled oscillator suchas 233₀ of a storage and unstuffing circuit 23₀ or 23₁ which is assignedto a 8 Mb/s signal to be demultiplexed is equivalent to the 8 Mb/s clockof the time base 47₀,3 or 47₀,4 which is associated with thedemultiplexer 42₀,3 or 42₄,7 in the second stage XIV.

Each time base 47₀,3 or 47₀,4 of this invention comprises a divide-by-4circuit 471 which is connected to the timing signal output terminal suchas 2303₀ of the associated storage and unstuffing circuit 23₀ or 23₁, adivide-by-53 circuit 472, a divide-by-4 circuit 473 and an addresscircuit 475 which receives the frequencies from circuits 471, 472 and473. The output terminals 4750 and 4751 of the address circuit 475correspond to the output terminals 750 and 751 of the address circuit 75of FIG. 5. The terminal 4750 is connected to the write-in progressioninput terminal such as 4301₀ of the associated circuit 43₀ through 43₃or 43₄ through 43₇. The terminal 4751 is connected to the input terminalsuch as 4304₀ of the stuffing recognition circuit such as 4304₀ of theassociated circuit 43₀ through 43₇ or 43₄ through 43₇ to delete all thereceived filling bits per 848-bit frame of which the addresses aretransmitted on the terminal 4751.

In the second demultiplexing stage XIV, the digital information outputterminals such as 4302₀ of the eight storage and unstuffing circuits 43₀through 43₇ transmit eight outgoing plesiosynchronous component 2 Mb/ssignals and are connected to the eight code conversion and retimingcircuits 45₀ through 45₇ respectively which receive from the associatedcontrolled-voltage oscillator such as 433₀ via the terminal such as4303₀ the 2 Mb/s clock signal. Eight outgoing digital 2,048 Mb/schannels 46₀ through 46₇ extend from the code conversion and retimingcircuits 45₀ through 45₇ respectively. Two outgoing digital 8 Mb/schannels 56₂ and 56₃ extend from the code conversion and retimingcircuits 25₂ and 25₃.

As shown in FIG. 7, in the case of sixteen plesiosynchronous incomingdigital 2,048 Mb/s channels 1₀ through 1₁₅ to be multiplexed into anoutgoing digital 34 Mb/s channel 16 and an incoming digital 34 Mb/schannel 20 to be demultiplexed into sixteen plesiosynchronous incomingdigital 2,048 Mb/s channels 46₀ through 46₁₅, the storage and unstuffingcircuit 23_(i), the demultiplexer 42_(4i),4i+3 and the time base47_(4i),4i+3 which are associated to four outgoing digital 2 Mb/schannels 46_(4i) through 46_(4i+3) are disposed on a common card 80_(i).The four stuffed outgoing digital 8 Mb/s signals are transmitted fromthe storage and stuffing circuit 13 to the multiplexer 14 of the secondmultiplexing stage XII via the respective card 80₀ through 80₃. Thus theoutput terminal 1302i of the circuit 13 is connected to the input accessterminal 800_(i) of the card 80_(i) and the output access terminal810_(i) of the card 80_(i) is connected to the digital information inputterminal 1410_(i) of the multiplexer 14, the card 80_(i) performing asingle by-pass conductor between the access terminal 800_(i) and810_(i).

In referring to FIG. 8 which concerns the multiplexing of eightplesiosynchronous incoming digital 2,048 Mb/s channels 1₀ through 1₇ andtwo plesiosynchronous incoming digital 8 Mb/s channels 11₂ and 11₃ intoan outgoing digital 34 Mb/s channel 16 and the demultiplexing of anincoming digital 34 Mb/s channel 20 into eight plesiosynchronousincoming channels 46₀ through 46₇ and two plesiosynchronous incomingchannels 56₂ and 56₃, the code conversion and timing or retimingcircuits 12_(j) and 25_(j) and the storage and stuffing or unstuffing13_(j) and 23_(j) which are associated with incoming and outgoing 8 Mb/schannels 11_(j) and 56_(j) are also disposed on a common card 81_(j).Four cards of this type are furthermore included in a multiplexing anddemultiplexing system embodying this invention which is associated withfour plesiosynchronous bidirectional 8 Mb/s channels. To replace a groupof four plesiosynchronous bidirectional 2 Mb/s channels by abidirectional 8 Mb/s channel in the resulting 34 Mb/s signal, itsuffices to replace a card 80_(i) by a card 81_(j). These two card typeshave a same interface with the circuits 14, 17, 22 and 27.

When a card 81_(j) is used, the link between the output terminal 1302jof the storage and stuffing circuit 13 and the input terminal 1420_(j)of the multiplexer 14 is cut off. In contrast, on the card 80_(j) theaccess terminal 810_(j) is connected to the associated output terminal1302j of the storage and stuffing circuit 13. Thus the multiplexer 14receives on its digital information input terminal 1410_(j) the stuffedincoming 8 Mb/s signal from the incoming channel 11_(j). At thedemultiplexing, the unstuffed outgoing 8 Mb/s signal from the associatedstorage and unstuffing circuit 23_(j) is transmitted into the codeconversion and retiming circuit 25_(j) and therefore there is notdemultiplexing of the associated unstuffed 8 Mb/s signal.

Although the invention has been described in accordance with particularembodiments and with reference to specific digital rates, variants whichcan readily be divised by the shilled addressee are of course possibleand fall within the invention as defined by the appended claims.

What we claim is:
 1. A digital multiplexing and demultiplexing system inwhich incoming plesiosynchronous signals are time multiplexed bit by bitinto synchronous intermediate rate signals and a number of incomingplesiosynchronous intermediate rate signals are time multiplexed bit bybit with said synchronous intermediate rate signals into an outgoingsignal high rate signal having a high rate which is a multiple of theoriginating intermediate rates, said plesiosynchronous low rate signalsand said plesiosynchronous intermediate rate signals comprising onlyinformation bits and said synchronous intermediate rate signals and saidhigh rate signal comprising information bits, stuffing bits and fillingbits including framing bits, service bits and stuffing indication bitsarranged in predetermined bit positions in frames, the systemcomprising;(a) first means for storing and stuffing said incomingplesiosynchronous low rate component signals in dependence upon thedifference between their own originating respective low rates and saidpredetermined low rate; (b) multiplexing means receiving andmultiplexing said predetermined low rate stuffed signals into frames ofsaid synchronous intermediate rate signals; (c) means for filling intosaid synchronous intermediate rate signals a first number of fillingbits of predetermined addresses of the frame forming synchronousintermediate rate filled signals; (d) second means for storing saidsynchronous intermediate rate filled signals and third means for storingsaid incoming plesiosynchronous intermediate rate component signals; (e)second means for stuffing said stored synchronous intermediate ratefilled signals and third means for stuffing said storedplesiosynchronous intermediate rate component signals in dependence uponthe difference between the originating intermediate rates and saidpredetermined intermediate rate; (f) multiplexing means connected tosaid second and third stuffing means for multiplexing the predeterminedintermediate rate stuffed signals into frames of the high rate signals;(g) means for filling into said high rate signal a second number offilling bits in bit positions of predetermined addresses of the framethereof and thereby forming a high rate filled signals; (h) firstdemultiplexing means receiving and demultiplexing said high rate filledsignal into first and second numbers of synchronous intermediate ratesignals; (i) first storing and unstuffing means for storing the firstnumber of synchronous intermediate rate demultiplexed signals and forextracting filling bits of predetermined addresses of high rate signalframe and for unstuffing into synchronous intermediate rate filledsignals; (j) second storing and unstuffing means for storing the secondnumber of synchronous intermediate rate demultiplexed signals forextracting filling bits of predetermined addresses of high rate signalframes and for unstuffing into outgoing plesiosynchonous intermediaterate component signals; (k) second demultiplexing means receiving anddemultiplexing said synchronous intermediate rate filled signals readout of said first storing and unstuffing means into synchronous low ratesingnals; (l) third storing and unstuffing means for storing synchronouslow rate signals and for extracting filling bits of predeterminedaddresses of intermediate rate signal frames and for unstuffing intooutgoing plesiosynchronous low rate component signals; (m)interchangeable assembling means for replacing a group of incoming andoutgoing plesiosynchronous low rate component signals by two incomingand outgoing plesiosynchonous intermediate rate component signals insaid high rate filled signal; and (n) said assembling means includingseparate storing means for incoming low rate signals and forintermediate rate signals and further including interconnecting meanbetween said separate storing mean and said first, second and thirdstoring and unstuffing means.